Parasitic Gate Leakage Testing
Electro thermally Induced Parasitic Gate Leakage is a trapped-charge Si-integrated circuit phenomenon failure mode introduced in high temperature, high electric field environments such as in an automotive engine compartment. Gate Leakage may occur in plastic encapsulated bipolar and CMOS technologies. It can adversely affect the performance and reliability of these integrated circuits. The gate leakage failure mode is reversible by an unbiased high temperature bake. Testing for gate leakage entails a high temperature bake process under the presence of a high electric field. Silicon Cert Laboratories conducts the gate leakage test to the standardized test (AEC-Q100-006). Tested samples are returned to the customer in cold-pack containers to preserve any possible accumulated charges from dissipating prior to electrical testing. Contact our engineering staff at Silicon Cert Laboratories to discuss your Parasitic Gate Leakage Testing requirements.
Test Specifications / Standards AEC Q100-006