Test Specifications / Standards

  • JSTD-002 
  • AEC-Q100
  • Solderability AEC-Q101 
  • AEC-Q200
  • MIL-STD-883, Method 2003
  • MIL-STD-750, Method 2026

Solderability Testing

Solderability testing provides a means of determining the solderability of device package terminations that are intended to be joined to another surface using SnPb or Pb-free solder. The procedure, considered to be destructive, will test whether the packaging materials and processes used during the manufacturing operations produce a component that can be successfully soldered in the next level assembly.

There are two methods of solderability testing. Method 1 is known as “dip and look” which is for leaded and leadless terminations. This method includes pre-conditioning if applicable, the application of flux, and the immersion of the terminations into molten solder. Method 2 is a Surface Mount Process Simulation test.

Test standards MIL-STD-883 and JSTD-002 reference preconditioning for the purpose of assessing the solderability of device package terminations by the user. While optional, an accelerated precondition is generally used prior to solderability testing to simulate package shipment and storage. These options, to be agreed upon between the user and the supplier, include steam conditioning or dry bake.

The inspection and failure criteria that Silicon Cert Laboratories follows requires

      a) all flux to be removed prior to inspection of the terminal surface,

      b) the devices to be inspected at 10x to 20x magnification, and

      c) the inspected area of each lead to have a minimum of 95% solder coverage.